multiplexer Diposting oleh Dian hermawan..... , Senin, 25 Oktober 2010 at 06.14, in

library ieee;
use ieee.std_logic_1164.all;

entity gede is
port(
a,b,c,d,s1,s2: in bit;
y:out bit);
end gede;

architecture idunk of gede is
begin
proc: process is
begin
if (s1='0' and s2='0') then y <= a; else if (s1='0' and s2='1') then y <= b; else if (s1='1' and s2='0') then y <= c; else if (s1='1' and s2='1') then y <= d; end if; end process proc; end idunk; entity sinyal is port( pa,pb,pc,pd,ps1,ps2:out bit); end sinyal; architecture sinyal_arch of sinyal is begin pros: process is begin pa <= '0'; pb <= '1'; pc <='1'; pd <= '0'; ps1 <= '1'; ps2 <= '0'; end process pros; end sinyal_arch; library work; use work.all; entity eksekusi is end eksekusi; architecture eksekusi_arch of eksekusi is signal in1,in2,in3,in4,select1,select2,output: bit; begin w1: entity sinyal port map(in1,in2,in3,in4,select1,select2); w2: entity kepletex port map(in1,in2,in3,in4,select1,select2,output); end eksekusi_arch;